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PIC16F87X

DS30292C-page 114

2001 Microchip Technology Inc.

11.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 11-2. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), see

Figure 11-2. The maximum recommended imped-

ance for analog sources is 10 k

. As the impedance

is decreased, the acquisition time may be decreased.

After the analog input channel is selected (changed),

this acquisition must be done before the conversion

can be started.

calculate

the

minimum

acquisition

time,

Equation 11-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

To calculate the minimum acquisition time, TACQ, see

the

PICmicro

Mid-Range

Reference

Manual

(DS33023).

EQUATION 11-1:

ACQUISITION TIME

FIGURE 11-2:

ANALOG INPUT MODEL

TACQ

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficient

TAMP + TC + TCOFF

s + TC + [(Temperature -25°C)(0.05s/°C)]

CHOLD (RIC + RSS + RS) In(1/2047)

- 120pF (1k

+ 7k + 10k) In(0.0004885)

16.47

s + 16.47s + [(50°C -25°C)(0.05s/°C)

19.72

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k

. This is required to meet the pin leak-

age specification.

4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.

During this time, the holding capacitor is not connected to the selected A/D input channel.

CPIN

ANx

5 pF

VDD

VT = 0.6V

I LEAKAGE

RIC

≤ 1k

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567 8 9 10 11

)

VDD

= 120 pF

± 500 nA

Legend

CPIN

I LEAKAGE

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

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